View ST8024T_4657329.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST8024T com/seg lcd driver datasheet note: sitronix technology corp. reserves the right to change the contents in this document without prior notice. this is not a final specification. some parameters are subject to change. version 0. 12 200 8/01/24 p r e l i m i n a r y
ST8024T preliminary ver 0. 12 page 2/ 26 200 8/ 01 /24 1. features number of lcd drive outputs: 240 supply voltage for lcd drive: +15.0 to + 30 .0 v supply voltage for the logic system: +2.5 to +5.5 v low power consumption low output impedance (segment mode) shift clock frequency 15mhz(max.): v dd = +5.0 0.5v 12mhz(max.): v dd = +3.0 to + 4.5v 8mhz(max.): v dd = +2.5 to + 3.0v adopts a data bus system 4- bit/8-bit parallel input modes are selectable with a mode (md) pin automatic transfer function of an enable signal automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data line latch circuits are reset when /dispoff active (common mode) shift clock frequency: 4 mhz (max.) built-in 240-bit b i- directional shift register (divisible into 120 bits x 2) available in a single mode (240-bit shift register) or in a dual mode (120-bit shift register x 2) y 1 ->y 240 single mode y 240 ->y 1 single mode y 1 ->y l20 , y 121 ->y 240 dual mode y 240 ->y 121 , y l20 ->y 1 dual mode the above 4 shift directions are pin-selectable shift register circuits are reset when /dispoff active 2. description the ST8024T is a 240-output segment/common driver ic suitable for driving large/medium scale dot matrix lcd panels, and is used in personal computers/work stations. the ST8024T is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution lcd.
ST8024T preliminary ver 0. 12 page 3/ 26 200 8/01/24 3. block diagram 4. functional operations of each block block function active control in case of segment mode, controls the selection or non-selection of the chip. following an lp signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. in case of common mode, controls the input/output data of bi-directional pins. sp conversion & data control in case of segment mode, keeps input data which are 2 clocks of xck at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of xck at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. data latch control in case of segment mode, selects the state of the data latch which reads in the data bus s ignals. the shift direction is controlled by the control logic. for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. data latch in case of segment mode, latches the data on the data bus. the latch state of each lcd drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. line latch/ shift register in case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the lp signal, and are output to the level shifter block. in case of common mode, shifts data from the data input pin at the falling edge of the lp signal. level shifter the logic voltage signal is level-shifted to the lcd drive voltage level, and is output to the driver block. 4- level driver drives the lcd drive output pins from the line latch/shift register data, and selects one of 4 levels (v 0 , v 12 , v 43 or vss) based on the s/c, fr and /dispoff signals. control logic controls the operation of each block. in case of segment mode, when an lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. in case of common mode, controls the direction of data shift. 240-bit 4-level driver 240-bit level shifter 240-bit line latch/shift register data control sp conversion & data control (4 to 8 or 8 to 8) control logic active control level shifter 8 bit data latch di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 v dd v ss v ss v 43l v 12l v 0l y 240 y 239 y 2 y 1 v ss v 43r v 12r v 0r fr /dispoff eio 1 eio 2 lp xck l/r md s/c 8 16 16 16 240 240
ST8024T preliminary ver 0. 12 page 4/ 26 200 8/01/24 5. pin description (tcp type) ps : detail size see tcp drawing data symbol i/o description y 1 -y 240 o lcd drive output v 0l , v 0r p power supply for lcd drive v 12l , v 12r p power supply for lcd drive v 43l , v 43r p power supply for lcd drive l/r i display data shift direction selection v dd p power supply for logic system (+2.5 to +5.5 v) s/c i segment mode/common mode selection eio 2 , eio 1 i/o input/output for chip selection at segment mode s hift data input/output for shift register at common mode di 0 -di 6 i display data input at segment mode di 7 i display data input at segment mode/dual mode data input at common mode xck i clock input for taking display data at segment mode /dispoff i control input for output of non-select level lp i latch pulse input for display data at segment mode/ shift clock input for shift register at common mode fr i ac-converting signal input for lcd drive waveform md i 4 or 8 bits mode selection input v ss p ground (0 v) test1,test2 i c onnect to gnd or floating
ST8024T preliminary ver 0. 12 page 5/ 26 200 8/01/24 6. input /output circuits i v dd to internal circuit gnd (0v) applicable pins l/r , s/c , di 6 ~di 0 , /dispoff , lp , fr , md figure 1 input circuit (1) figure 2 input circuit (2) i v dd to internal circuit applicable pins di 7 , xck gnd (0v) gnd (0v) control signal
ST8024T preliminary ver 0. 12 page 6/ 26 200 8/01/24 figure 3 input/output circuit figure 4 lcd drive output circuit o gnd (0v) v 0 control signal 1 control signal 3 control signal 2 control signal 4 v 0 v 12 v 43 v ss gnd (0v) application pins y 1 ~y 160 v dd i/o to internal circuit gnd (0v) gnd (0v) control signal gnd (0v) v dd output signal control signal application pins eio 1 , eio 2
ST8024T preliminary ver 0. 12 page 7/ 26 200 8/01/24 7. functional description 7.1 pin functions (segment mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. gnd ground pin lgnd logic ground pin do not short lgnd with gnd and vss by ito on lcd panel connect it to gnd on pcb or fpc. v ss connect to gnd by ito on lcd panel. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage normally use the bias voltages set by a resistor divider ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin di 7 -di 0 input pins for display data in 4-bit parallel mode, di 3 -di 0 are the display data input pins, and di 7 -di 4 must be connected to lgnd or v dd . in 8-bit parallel mode, all di 7 -dl 0 pins are the display data input pins. refer to section 7.2.2. xck clock input pin for taking display data data is read at the falling edge of the clock pulse. lp latch pulse input pin for display data data is latched at the falling edge of the clock pulse. l/r input pin for selecting the reading direction of display data when set to lgnd level "l", data is read sequentially from y 240 to y 1 . when set to v dd level "h", data is read sequentially from y 1 to y 240 . refer to section 7.2.2. /dispoff control input pin for output of non-select level the input signal is level-shifted from logic voltage level to lcd drive voltage level, and contro ls the lcd drive circuit. when set to lgnd level "l", the lcd drive output pins (y 1 -y 240 ) are set to level vs s. when set to "l", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /dispoff. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), then outputs the contents of the data latch at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, it can not output the reading data correctly. table of truth values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. normally it inputs a frame inversion signal. the lcd drive output pins' output voltage levels can be set using the line latch output signal and the fr signal. table of truth values is shown in "truth table" in functional operations. md mode selection pin when set to lgnd level "l", 8-bit parallel input mode is set. when set to v dd level "h", 4-bit parallel input mode is set. refer to section 7.2.2. s/c segment mode/common mode selection pin when set to v dd level "h", segment mode is set. elo 1 , eio 2 input/output pins for chip selection when l/r input is at lgnd level "l", elo 1 is set for output, and eio 2 is set for input. when l/r input is at v dd level "h", elo 1 is set for input, and eio 2 is set for output.
ST8024T preliminary ver 0. 12 page 8/ 26 200 8/01/24 during output, set to "h" while lp ? xck is "h" and after 240 bits of data have been read, set to "l? for one cycle (from falling edge to failing edge of xck), after which it returns to "h". during input, the chip is selected while el is set to "l" after the lp signal is input. the chip is non-selected after 240 bits of data have been read. y 1 -y 240 lcd drive output pins corresponding directly to each bit of the data latch, one level (v 0 , v 12 , v 43 , or v ss ) is selected and output. table of truth values is shown in "truth table" in functional operations. (common mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. gnd ground pin lgnd logic ground pin do not short lgnd with gnd and vss by ito on lcd panel connect it to gnd on pcb or fpc. v ss connect to gnd by ito on lcd panel. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage normally use the bias voltages set by a resistor divider. ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. elo 1 shift data input/output pin for bi-directional shift register output pin when l/r is at lgnd level "l', input pin when l/r is at v dd level "h". when l/r = h, elo 1 is used as input pin, it will be pulled down. when l/r = l, elo 1 is used as output pin, it won't be pulled down. refer to section 7.2.2. eio 2 shift data input/output pin for bi-directional shift register input pin when l/r is at lgnd level "l", output pin when l/r is at v dd level "h". when l/r = l, eio 2 is used as input pin, it will be pulled down. when l/r = h, eio 2 is used as output pin, it won't be pulled down. refer to section 7.2.2. lp shift clock pulse input pin for bi-directional shift register data is shifted at the falling edge of the clock pulse. l/r input pin for selecting the shift direction of bi-directional shift register data is shifted from y 240 to y 1 when set to lgnd level "l", and data is shifted from y 1 to y 240 when set to v dd level "h". refer to section 7.2.2. /dispoff control input pin for output of non-select level the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. when set to lgnd level "l", the lcd drive output pins (y 1 -y 240 ) are set to level lgnd. w hen set to "l?, the contents of the shift register are reset to not reading data. when the /dispoff function is canceled, the driver outputs non -s elect level (v 12 or v 43 ), and the shift data is read at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, the shift data is not read correctly. table of truth values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. normally it inputs a frame inversion signal. the lcd drive output pins' output voltage levels can be set using the shift register output signal and the fr signal. table of truth values is shown in "truth table" in functional operations. md mode selection pin when set to lgnd level "l", single mode operation is selected; when set to v dd level
ST8024T preliminary ver 0. 12 page 9/ 26 200 8/01/24 "h" dual mode operation is selected. refer to section 7.2.2. di 7 dual mode data input pin according to the data shift direction of the data shift register, data can be input starting from the 121st bit. when the chip is used in dual mode, di 7 will be pulled down. when the chip is used in single mode, di 7 won't be pulled down. refer to section 7.2.2. s/c segment mode/common mode selection pin when set to lgnd level "l", common mode is set. di 6 -di 0 not used connect di 6 -di 0 to lgnd or v dd , avoiding floating. xck not used xck is pulled down in common mode, so connect to lgnd or open. y 1 -y 240 lcd drive output pins corresponding directly to each bit of the shift register, one level (v 0 , v 12 , v 43 , or v ss ) is selected and output. table of truth values is shown in "truth table" in functional operations. 7.2 functional operations 7.2.1 truth table (segment mode) fr latch data /d ispoff lcd drive output voltage level (y1-y240) l l h v 43 l h h v ss h l h v 12 h h h v 0 x x l v ss (common mode) fr latch data /d ispoff lcd drive output voltage level (y1-y240) l l h v 43 l h h v 0 h l h v 12 h h h v ss x x l v ss notes: v ss < v 43 < v 12 < v 0 l: lgnd (0 v), h: v dd (+2.5 to +5.5 v), x: don't care "don't care" should be fixed to "h" or "l", avoiding floating. there are two kinds of power supply (logic level voltage and lcd drive voltage) for the lcd driver. supply regular voltage which is assigned by specification for each power pin.
ST8024T preliminary ver 0. 12 page 10/26 200 8/01/24 7.2.2 relationship between the display data and lcd drive output pins (segment mode) (a) 4- bit parallel input mode number of clocks md l/r eio 1 ei0 2 data input 60 clock 59 clock 58 clock ? 3 clock 2 clock 1 clock di 0 y 1 y 5 y 9 ? y 229 y 233 y 237 dl 1 y 2 y 6 y 10 ? y 230 y 234 y 238 di 2 y 3 y 7 y 11 ? y 231 y 235 y 239 h l output input di 3 y 4 y 8 y 12 ? y 232 y 236 y 240 di 0 y 240 y 236 y 232 ? y 12 y 8 y 4 dl 1 y 239 y 235 y 231 ? y 11 y 7 y 3 di 2 y 238 y 234 y 230 ? y 10 y 6 y 2 h h input output di 3 y 237 y 233 y 229 ? y 9 y 5 y 1 (b) 8- bit parallel input mode number of clocks md l/r eio 1 ei0 2 data input 30 clock 29 clock 28 clock ? 3 clock 2 clock 1 clock di 0 y 1 y 9 y 17 ? y 217 y 225 y 233 dl 1 y 2 y 10 y 18 ? y 218 y 226 y 234 di 2 y 3 y 11 y 19 ? y 219 y 227 y 235 di 3 y 4 y 12 y 20 ? y 220 y 228 y 236 di 4 y 5 y 13 y 21 y 221 y 229 y 237 di 5 y 6 y 14 y 22 y 222 y 230 y 238 di 6 y 7 y 15 y 23 y 223 y 231 y 239 l l output input di 7 y 8 y 16 y 24 y 224 y 232 y 240 di 0 y 240 y 232 y 224 ? y 24 y 16 y 8 dl 1 y 239 y 231 y 223 ? y 23 y 15 y 7 di 2 y 238 y 230 y 222 ? y 22 y 14 y 6 di 3 y 237 y 229 y 221 ? y 21 y 13 y 5 di 4 y 236 y 228 y 220 ? y 20 y 12 y 4 dl 5 y 235 y 227 y 219 ? y 19 y 11 y 3 di 6 y 234 y 226 y 218 ? y 18 y 10 y 2 l h input output di 7 y 233 y 225 y 217 ? y 17 y 9 y 1 (common mode) md l/r data transfer direction eio 1 ei0 2 di 7 l y 240 y 1 output input x l (single) h y 1 y 240 input output x y 240 y 121 l y 120 y 1 output input input y 1 y 120 h (dual) h y 121 y 240 input output input notes: l: lgnd (0 v), h: v dd (+2.5 to +5.5 v), x: don't care "don't care" should be fixed to "h" or "l", avoiding floating.
ST8024T preliminary ver 0. 12 page 11/26 200 8/01/24 7.2.3 connection examples of plural segment drivers (a) when l/r = ?l? y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 xck lp md fr di 7 -di 0 xck lp md fr di 7 -di 0 xck lp m d fr di 7 -di 0 xck lp md fr di 7 -di 0 l/r l/r l/r lgnd 8 top data last data data flow (b) when l/r = ?h? y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 xck lp md fr di 7 -di 0 xck lp md fr di 7 -di 0 l/r l/r l/r v dd 8 top data last data data flow xck lp md fr di 7 -di 0 xck lp md fr di 7 -di 0 lgnd
ST8024T preliminary ver 0. 12 page 12/26 200 8/01/24 7.2.4 timing chart of 4-device cascade connection of segment drivers n* n* n* n* n* 1 1 1 1 1 22222 device a device b device c device d top data last data *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode eo (device c) eo (device b) eo (device a) ei (device a) di 7 - di 0 xck lp fr
ST8024T preliminary ver 0. 12 page 13/26 200 8/01/24 7.2.5 connection examples for plural common drivers (a) single mode (l/r = ?l?) (b) single mode (l/r = ?h?) y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 fr l/r /dispoff md fr di 7 lp /dispoff lgnd (v dd ) first last lp lgnd v dd flm l/r /dispoff md fr di 7 lp l/r /dispoff md fr di 7 lp y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 lp lgnd fr /dispoff l/r lp md fr lgnd(v dd ) first last flm /dispoff l/r lp md fr di 7 /dispoff l/r lp md fr di 7 /dispoff di 7
ST8024T preliminary ver 0. 12 page 14/26 200 8/01/24 (c) dual mode (l/r = ?l?) y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 lp lgnd fr /dispoff l/r lp md fr di 7 lgnd (v dd ) first last 2 flm1 /dispoff l/r lp md fr di 7 /dispoff l/r lp md fr di 7 /dispoff first 2 last 1 y 121 y 120 flm2 v dd (d) dual mode (l/r = ?h?) y 240 y 240 y 240 y 1 y 1 y 1 eio2 eio2 eio2 eio1 eio1 eio1 fr l/r /dispoff md fr di 7 lp /dispoff lgnd (v dd ) first 1 last 2 lp lgnd v dd flm1 l/r /dispoff md fr di 7 lp l/r /dispoff md fr di 7 lp last 1 first 2 y 120 y 121 flm2
ST8024T preliminary ver 0. 12 page 15/26 200 8/01/24 8. precautions precautions when connecting or disconnecting the power supply this ic has a high-voltage lcd driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating. the details are as follows, when connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd drive power it is advisable to connect the serial resistor (50 to 100 ) or fuse to the lcd drive power v 0 of the system as a current limiter. set up a suitable value of the resistor in consideration of the display grade. and when connecting the logic power supply, the logic condition of this ic inside is insecure. therefore connect the lcd drive power supply after resetting logic condition of this ic inside on /dispoff function. after that, cancel the /dispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level lgnd on /dispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here . v dd lgnd v dd lgnd v 0 gnd v dd /dispoff v 0
ST8024T preliminary ver 0. 12 page 16/26 200 8/01/24 9. absolute maximum ratings parameter symbol applicable pins r ating unit note supply voltage (1) v dd v dd -0.3 to +7.0 v v 0 v 0l , v 0r -0.3 to +33.0 v v 12 v 12l , v 12r -0.3 to v 0 + 0.3 v v 43 v 43l , v 43r -0.3 to v 0 + 0.3 v supply voltage (2) v ss v ss -0.3 to v 0 + 0.3 v input voltage v i di 7 -di 0 , xck, lp, l/r, fr, md, s/c, eio 1 , e io 2 , /dispoff -0.3 to v dd + 0.3 v 1,2 storage temperature t stg -45 to +125 c notes: 1. ta = +25 c 2. the applicable voltage on logic pins with respect to lgnd, high voltage pins with v ss (0 v). 10. recommended operating conditions parameter symbol applicable pins min. t yp. max. unit note supply voltage (1) v dd v dd +2.5 +5.5 v supply voltage (2) v 0 v 0l , v 0r +15.0 +30.0 v 1 , 2 operating temperature t opr -25 +70 c notes: 1. the applicable voltage on logic pins with respect to lgnd, high voltage pins with v ss (0 v). 2. ensure that voltages are set such that v ss < v 43 < v l2 < v 0 .
ST8024T preliminary ver 0. 12 page 17/26 200 8/01/24 11. electrical characteristics 11.1 dc characteristics (segment mode) (lgnd=v ss =gnd = 0v, v dd = +2.5 ~ +5.5 v, v 0 = + 15.0 ~ + 30 .0v, t opr = -25 to +70c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l /r, fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = lgnd -10.0 a input leakage current i lih v i = v dd di 7 -di 0 , xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , /dispoff +10.0 a v 0 =30v 1.5 2.0 output resistance r on | v on | =0 . 5v v 0 =20v y 1 -y 240 2.0 2.5 k standby current i stb lgnd+gnd+vss 75.0 a 1 supply current (1) (non-selection) i dd1 v dd 2.0 ma 2 supply current (2) (selection) i dd2 v dd 12.0 ma 3 supply current (3) i 0 v 0l , v 0r 1.5 ma 4 notes: 1. v dd = +5.0 v, v 0 = +30.0 v, vi = lgnd. 2. v dd = +5.0 v, v 0 = +30.0 v, f xck = 15 mhz, no-load, el = v dd . the input data is turned over by data taking clock (4-bit parallel input mode). 3. v dd = +5.0 v, v 0 = + 30 .0 v, f xck = 15 mhz, no-load, el = lgnd. the input data is turned over by data taking clock (4-bit parallel input mode). 4. v dd = +5.0 v, v 0 = +30.0 v, f xck = 15mhz, f lp = 20.8 khz, f fr = 80 hz, no-load. the input data is turned over by data taking clock (4-bit parallel input mode). (common mode) (lgnd=v ss =gnd = 0v, v dd = +2.5 ~ +5.5v, v 0 = + 15.0 ~ + 30 .0v, t opr = -25 to +70 c) parameter symbol cond itions applicabl e pi ns mi n. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l/r fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = lgnd di 7 -di 0 , xck, lp, l/r fr, md, s/c, eio 1 , eio 2 , /dispoff -10.0 a input leakage current i lih v i = v dd di 6 -di 0 , lp, l/r, fr, md, s/c, /dispoff +10.0 a input pull-down current i pd v i = v dd di 7 , xck, eio 1 , eio 2 100.0 a v 0 =30v 1.5 2.0 output resistance r on | v on | =0 . 5v v 0 =20v y 1 -y 240 2.0 2.5 k standby current i spd lgnd+gnd+vss 75.0 a 1 supply current (1) i dd v dd 120.0 a 2 supply current (2) i 0 v 0l , v 0r 240.0 a 2 notes: 1. v dd = +5.0 v, v 0 = +30.0 v, v i = lgnd 2. v dd = +5.0 v, v 0 = + 30 .0 v, f lp = 20.8 khz, f fr = 80 hz, 1/480 duty operation, no-load.
ST8024T preliminary ver 0. 12 page 18/26 200 8/01/24 11.2 ac characteristics (segment mode 1) (lgnd=v ss = gnd = 0 v, v dd = +5.00.5 v, v 0 = + 15.0 ~ + 30 .0v, t opr = -25 to +70 c) parameter symbol condi tions min t yp. max. unit note shift clock period t wck t r ,t f 10ns 66 ns 1 shift clock "h" pulse width t wckh 23 ns shift clock "l" pulse width t wckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 41 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (segment mode 2) (lgnd=v ss =gnd = 0v, v dd = +3.0 ~ +4.5v, v 0 = + 15.0 ~ + 30 .0v, t opr = -25 to +70 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 82 ns 1 shift clock "h" pulse width t wckh 28 ns shift clock "l? pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 65 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 57 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation.
ST8024T preliminary ver 0. 12 page 19/26 200 8/01/24 (segment mode 3) (lgnd=v ss =gnd = 0v, v dd = +2.5 ~ +3.0v, v 0 = + 15.0 ~ + 30 .0v, t opr = -25 to+70 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 130 ns 1 shift clock "h" pulse width t wckh 35 ns shift clock "l? pulse width t wckl 35 ns data setup time t ds 25 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 80 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 80 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (common mode) (lgnd=v ss = 0 v, v dd = +2.5 ~ +5.5v, v 0 = +15.0 ~ + 30 .0v, t opr = -25 to +70 c) parameter symbol conditions m in. typ. max. unit shift clock period t wlp t r ,t f 20ns 250 ns v dd = +5.0 0.5v 15 ns shift clock "h" pulse width t wlph v dd = +2.5+ 4.5v 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t dl cl = 15 pf 200 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s
ST8024T preliminary ver 0. 12 page 20/26 200 8/01/24 11.3 timing chart of segment mode fr lp /dispoff y 1 - y 240 t pd1 t pd3 t pd2 fig. 8 timing characteristics (3) lp xck di 7 - di 0 /dispoff t wlph t ld t sl t lh t ls t wckh t f t r t wck t ds t dh top data last data t wdl t sd t wckl t s 12 n* t d lp xck ei eo *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode
ST8024T preliminary ver 0. 12 page 21/26 200 8/01/24 11.4 timing chart of common mode lp eio 2 eio 1 /dispoff t wdl t sd t dl t h t su t wlp t r t wlph t f fr lp /dispoff y 1 - y 240 t pd1 t pd3 t pd2
ST8024T preliminary ver 0. 12 page 22/26 200 8/01/24 12. application circuit 12.1 application circuit for module
ST8024T preliminary ver 0. 12 page 23/26 200 8/01/24 13. pad diagram unit : um pad# name x y p ad# name x y p ad# name x y 1 v0l - 6437.25 266.85 33 dummy - 1525.35 - 263.10 65 vss 6437.25 - 266.85 2 v0l - 6437.25 207.55 34 dummy - 1360.40 - 263.10 66 vss 6437.25 - 207.55 3 v0l - 6437.25 148.25 35 dum my - 1195.45 - 263.10 67 v34r 6437.25 - 148.25 4 v0l - 6437.25 88.95 36 dummy - 874.05 - 263.10 68 v34r 6437.25 - 88.95 5 v12l - 6437.25 29.65 37 dummy - 527.80 - 224.40 69 v12r 6437.25 - 29.65 6 v12l - 6437.25 - 29.65 38 dummy - 161.08 - 227.68 70 v12r 6437.25 29.65 7 v34l - 6437.25 - 88.95 39 dummy 228.83 - 217.73 71 v0r 6437.25 88.95 8 v34l - 6437.25 - 148.25 40 dummy 614.43 - 217.73 72 v0r 6437.25 148.25 9 vss - 6437.25 - 207.55 41 dummy 878.05 - 220.48 73 v0r 6437.25 207.55 10 vs s - 6437.25 - 266.85 42 dummy 1297.05 - 263.10 74 v0r 6437.25 266.85 11 gnd - 6268.15 - 263.15 43 dummy 1474.50 - 263.10 75 dummy 6317.00 250.10 12 gnd - 6136.55 - 263.15 44 dummy 1651.95 - 263.10 76 y1 6267.00 250.10 13 dummy - 5978.15 -209.0 5 45 dummy 1829.40 - 263.10 77 y2 6215.00 250.10 14 lgnd - 5680.50 - 263.15 46 dummy 2006.85 - 263.10 78 y3 6163.00 250.10 15 lgnd - 5573.05 - 263.15 47 dummy 2184.30 - 263.10 79 y4 6111.00 250.10 16 vdd - 5452.80 - 263.15 48 dummy 2361.75 -2 63.10 80 y5 6059.00 250.10 17 vdd - 5345.35 - 263.15 49 dummy 2539.20 - 263.10 81 y6 6007.00 250.10 18 s/c - 5208.40 - 263.10 50 di6 2731.90 - 263.10 82 y7 5955.00 250.10 19 eio2 - 4786.70 - 263.10 51 di7 2893.20 - 263.10 83 y8 5903.00 250.10 20 dummy - 4412.48 - 263.10 52 xck 3214.45 - 263.10 84 y9 5851.00 250.10 21 di0 - 4005.45 - 263.10 53 /dispoff 3505.05 - 263.10 85 y10 5799.00 250.10 22 di1 - 3621.55 - 263.10 54 dummy 3709.58 - 263.10 86 y11 5747.00 250.10 23 di2 - 3317.00 - 263.10 55 lp 4122.15 - 263.10 87 y12 5695.00 250.10 24 di3 - 3005.05 - 263.10 56 eio1 4450.75 - 263.10 88 y13 5643.00 250.10 25 di4 - 2840.45 - 263.10 57 fr 4806.65 - 263.10 89 y14 5591.00 250.10 26 di5 - 2679.15 - 263.10 58 l/r 5094.20 -263 .10 90 y15 5539.00 250.10 27 dummy - 2515.05 - 263.10 59 md 5349.25 - 263.10 91 y16 5487.00 250.10 28 dummy - 2350.10 - 263.10 60 lgnd 5573.05 - 263.15 92 y17 5435.00 250.10 29 dummy - 2185.15 - 263.10 61 lgnd 5680.50 - 263.15 93 y18 5383.00 250.10 30 dummy - 2020.20 - 263.10 62 dummy 5978.15 - 209.05 94 y19 5331.00 250.10 31 dummy - 1855.25 - 263.10 63 gnd 6136.55 - 263.15 95 y20 5279.00 250.10 32 dummy - 1690.30 - 263.10 64 gnd 6268.15 - 263.15 96 y21 5227.00 250.10
ST8024T preliminary ver 0. 12 page 24/26 200 8/01/24 97 y22 5 175 .00 250.10 148 y73 2523.00 250.10 199 y123 - 183.00 250.10 98 y23 5123.00 250.10 149 y74 2471.00 250.10 200 y124 - 235.00 250.10 99 y24 5071.00 250.10 150 y75 2419.00 250.10 201 y125 - 287.00 250.10 100 y25 5019.00 250.10 151 y76 2 367.0 0 250.10 202 y126 - 339.00 250.10 101 y26 4967.00 250.10 152 y77 2315.00 250.10 203 y127 - 391.00 250.10 102 y27 4915.00 250.10 153 y78 2263.00 250.10 204 y128 - 443.00 250.10 103 y28 4863.00 250.10 154 y79 2211.00 250.10 205 y129 -4 95. 00 250.10 104 y29 4811.00 250.10 155 y80 2159.00 250.10 206 y130 - 547.00 250.10 105 y30 4759.00 250.10 156 y81 2107.00 250.10 207 y131 - 599.00 250.10 106 y31 4707.00 250.10 157 y82 2055.00 250.10 208 y132 - 651.00 250.10 107 y32 4 655 .00 250.10 158 y83 2003.00 250.10 209 y133 - 703.00 250.10 108 y33 4603.00 250.10 159 y84 1951.00 250.10 210 y134 - 755.00 250.10 109 y34 4551.00 250.10 160 y85 1899.00 250.10 211 y135 - 807.00 250.10 110 y35 4499.00 250.10 161 y86 1 847 .00 250.10 212 y136 - 859.00 250.10 111 y36 4447.00 250.10 162 y87 1795.00 250.10 213 y137 - 911.00 250.10 112 y37 4395.00 250.10 163 y88 1743.00 250.10 214 y138 - 963.00 250.10 113 y38 4343.00 250.10 164 y89 1691.00 250.10 215 y139 -1 0 15.00 250.10 114 y39 4291.00 250.10 165 y90 1639.00 250.10 216 y140 - 1067.00 250.10 115 y40 4239.00 250.10 166 y91 1587.00 250.10 217 y141 - 1119.00 250.10 116 y41 4187.00 250.10 167 y92 1535.00 250.10 218 y142 - 1171.00 250.10 117 y42 4135.00 250.10 168 y93 1483.00 250.10 219 y143 - 1223.00 250.10 118 y43 4083.00 250.10 169 y94 1431.00 250.10 220 y144 - 1275.00 250.10 119 y44 4031.00 250.10 170 y95 1379.00 250.10 221 y145 - 1327.00 250.10 120 y45 3979.00 250.10 171 y96 1327.00 250.10 222 y146 - 1379.00 250.10 121 y46 3927.00 250.10 172 y97 1275.00 250.10 223 y147 - 1431.00 250.10 122 y47 3875.00 250.10 173 y98 1223.00 250.10 224 y148 - 1483.00 250.10 123 y48 3823.00 250.10 174 y99 1171.00 250.10 225 y149 - 1535.00 250.10 124 y49 3771.00 250.10 175 y100 1119.00 250.10 226 y150 - 1587.00 250.10 125 y50 3719.00 250.10 176 y101 1067.00 250.10 227 y151 - 1639.00 250.10 126 y51 3667.00 250.10 177 y102 1015.00 250.10 228 y152 - 1691.00 250.10 127 y52 3615.00 250.10 178 y103 963.00 250.10 229 y153 - 1743.00 250.10 128 y53 3563.00 250.10 179 y104 911.00 250.10 230 y154 - 1795.00 250.10 129 y54 3511.00 250.10 180 y105 859.00 250.10 231 y155 - 1847.00 250.10 130 y55 3 459. 00 250.10 181 y106 807.00 250.10 232 y156 - 1899.00 250.10 131 y56 3407.00 250.10 182 y107 755.00 250.10 233 y157 - 1951.00 250.10 132 y57 3355.00 250.10 183 y108 703.00 250.10 234 y158 - 2003.00 250.10 133 y58 3303.00 250.10 184 y109 6 51.00 250.10 235 y159 - 2055.00 250.10 134 y59 3251.00 250.10 185 y110 599.00 250.10 236 y160 - 2107.00 250.10 135 y60 3199.00 250.10 186 y111 547.00 250.10 237 y161 - 2159.00 250.10 136 y61 3147.00 250.10 187 y112 495.00 250.10 238 y162 - 2211.00 250.10 137 y62 3095.00 250.10 188 y113 443.00 250.10 239 y163 - 2263.00 250.10 138 y63 3043.00 250.10 189 y114 391.00 250.10 240 y164 - 2315.00 250.10 139 y64 2991.00 250.10 190 y115 339.00 250.10 241 y165 - 2367.00 250.10 140 y65 2939.00 250.10 191 y116 287.00 250.10 242 y166 - 2419.00 250.10 141 y66 2887.00 250.10 192 y117 235.00 250.10 243 y167 - 2471.00 250.10 142 y67 2835.00 250.10 193 y118 183.00 250.10 244 y168 - 2523.00 250.10 143 y68 2783.00 250.10 194 y119 131.00 250.10 245 y169 - 2575.00 250.10 144 y69 2731.00 250.10 195 y120 79.00 250.10 246 y170 - 2627.00 250.10 145 y70 2679.00 250.10 196 dummy 0.00 250.10 247 y171 - 2679.00 250.10 146 y71 2627.00 250.10 197 y121 - 79.00 250.1 0 248 y172 - 2731.00 250.10 147 y72 2575.00 250.10 198 y122 - 131.00 250.10 249 y173 - 2783.00 250.10 250 y174 - 2835.00 250.10 273 y197 - 4031.00 250.10 296 y220 - 5227.00 250.10
ST8024T preliminary ver 0. 12 page 25/26 200 8/01/24 251 y175 - 2887.00 250.10 274 y198 - 4083.00 250.10 297 y221 - 5279.00 250.10 252 y176 - 2939.00 250.10 275 y199 - 4135.00 250.10 298 y222 - 5331.00 250.10 253 y177 - 2991.00 250.10 276 y200 - 4187.00 250.10 299 y223 - 5383.00 250.10 254 y178 - 3043.00 250.10 277 y201 - 4239.00 250.10 300 y224 - 5435.00 2 50.10 255 y179 - 3095.00 250.10 278 y202 - 4291.00 250.10 301 y225 - 5487.00 250.10 256 y180 - 3147.00 250.10 279 y203 - 4343.00 250.10 302 y226 - 5539.00 250.10 257 y181 - 3199.00 250.10 280 y204 - 4395.00 250.10 303 y227 - 5591.00 250.10 258 y182 - 3251.00 250.10 281 y205 - 4447.00 250.10 304 y228 - 5643.00 250.10 259 y183 - 3303.00 250.10 282 y206 - 4499.00 250.10 305 y229 - 5695.00 250.10 260 y184 - 3355.00 250.10 283 y207 - 4551.00 250.10 306 y230 - 5747.00 250.10 261 y185 - 3407.00 250.10 284 y208 - 4603.00 250.10 307 y231 - 5799.00 250.10 262 y186 - 3459.00 250.10 285 y209 - 4655.00 250.10 308 y232 - 5851.00 250.10 263 y187 - 3511.00 250.10 286 y210 - 4707.00 250.10 309 y233 - 5903.00 250.10 264 y188 - 3563.00 2 50.10 287 y211 - 4759.00 250.10 310 y234 - 5955.00 250.10 265 y189 - 3615.00 250.10 288 y212 - 4811.00 250.10 311 y235 - 6007.00 250.10 266 y190 - 3667.00 250.10 289 y213 - 4863.00 250.10 312 y236 - 6059.00 250.10 267 y191 - 3719.00 250.10 290 y214 - 4915.00 250.10 313 y237 - 6111.00 250.10 268 y192 - 3771.00 250.10 291 y215 - 4967.00 250.10 314 y238 - 6163.00 250.10 269 y193 - 3823.00 250.10 292 y216 - 5019.00 250.10 315 y239 - 6215.00 250.10 270 y194 - 3875.00 250.10 293 y217 -5 07 1.00 250.10 316 y240 - 6267.00 250.10 271 y195 - 3927.00 250.10 294 y218 - 5123.00 250.10 317 dummy - 6317.00 250.10 272 y196 - 3979.00 250.10 295 y219 - 5175.00 250.10 13.1 gold bump size pad no. x y area (um 2 ) 1~10, 65~74 87.50 44.30 3876. 2500 11, 12 , 63, 64 116.60 42.30 4932.1800 13, 62 160.20 33.30 5334.6600 14~17, 60, 61 92.50 42.30 3912.7500 18, 19, 21~26, 50~53, 55~59 131.30 42.40 5567.1200 20, 54 152.35 42.40 6459.6400 27~36 134.30 42.40 5694.3200 37 94.30 44.40 4186.9200 38 103.85 37.85 3930.7225 39, 40 85.65 57.75 4946.2875 41 117.20 52.25 6123.7000 42~49 140.80 42.40 5969.9200 196 91.00 81.00 7371.0000 75, 317 33.00 81.00 2673.0000 76~195, 197~316 37.00 81.00 2997.0000 wafer thickness = 480 20um, bump pad height = 15um, strength=30g
ST8024T preliminary ver 0. 12 page 26/26 200 8/01/24 14. revision revision description p age date 0.10 first release 1-26 200 6/ 12 /11 0.11 change max. operating voltage to +30v change standby current application pin to lgnd+gnd+vss 1- 26 2007/04/20 0.12 change operating temperature to 70 c 16-19 2008/01/24 the above information is the exclusive intellectual property of sitronix technology corp. and shall not be disclosed, distributed or reproduced without permission from sitronix.

▲Up To Search▲

Price & Availability of ST8024T

	To Download ST8024T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .